on Emerging Trends in Engineering and Technology (ICETET), pp. Sharma, D.K., Kaushik, B.K., Sharma, R.K.: Effect of mutual inductance and coupling capacitance on propagation delay and peak overshoot in dynamically switching inputs. Roy, A., Mahmoud, N., Chowdhury, M.H.: Effects of coupling capacitance and inductance on delay uncertainty and clock skew. Ismail, Y.I., Friedman, E.G.: Effect of inductance on propagation delay and repeater insertion in VLSI circuits. 23(3), 55–63 (2006)Įlgamel, M.A., Bayoumi, M.A.: Interconnect noise analysis and optimization in deep submicron technology. Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.: Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects.
#Fdtd spice driver#
Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.: Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects. Kaushik, B.K., Sarkar, S.: Crosstalk analysis for a CMOS-gate-driven coupled interconnects. Roy, A., Xu, J., Chowdhury, M.H.: Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. on VLSI Technology Digest of Technical Paper, pp. Sylvester, D., Hu, C., Nakagawa, O.S., Oh, S.-Y.: Interconnect scaling: signal integrity and performance in future high speed CMOS design. Rabaey, J.M.: Digital Integrated Circuits, A Design Perspective. An average error of less than 2 % is observed for the proposed FDTD algorithm with respect to SPICE.
A good agreement of FDTD results has been observed with respect to SPICE results. To validate the proposed method, FDTD computations are carried out and results are compared with those of conventional SPICE results. To ensure stability in FDTD solution, the discrete voltage points are interlaced by current points in both space and time. For implementation of FDTD algorithm, discretizations are carried out in time and space both. The FDTD method is used because it is a strong mathematical platform for the analysis of time domain behavior of coupled lines. This paper analyzes the dependency of crosstalk noise and delay on coupling parasitics for simultaneously switching inputs using FDTD technique. The coupling parasitics ( M, C C) introduce crosstalk noise which may lead to critical delays/logic malfunctions. In UDSM technology, on-chip interconnect wires form a complex geometry and introduces wire and coupling parasitics.
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